When the power of a switched mode power supply (SMPS) integrated circuit (IC) starts operating, the current required to charge a capacitor in the system may produce significant input current requirements. If the current used is too high, the battery voltage may drop, thus leading to the devices in the system entering a reset state or providing an erratic operation.
To overcome the problem above, a soft-start scheme may be used to limit the current at a start-up phase. The current capability of the IC is slowly raised until full current capability is reached. Such schemes are typically used in many of present-day boost converters, for example.
Typical boost applications are tuned for ms range of a start-up time. However, this is not possible e.g. in multi-mode cellular phone transmitters in which the wake-up time of an individual block before e.g. a transmission (TX) slot is limited; thus, a very fast rise time is mandatory. Therefore it is beneficial to use such an arrangement of power switches which allows an output voltage to be pre-charged whenever the battery voltage is available. However, this makes the wake-up phase different from a very basic application, when it is a question of boost converter topology arrangements.
When switches are arranged as in the example of FIG. 1, the initial output voltage is battery voltage minus 300 . . . 400 mV due to a so-called body-diode of an NLDEMOS (N-type lateral double diffused with drain extension metal-oxide switch transistor). Thus, without this kind of arrangement, an in-rush current would be huge if minimum rise time of the boost converter was needed and an output voltage was started from 0V. However, after an initial phase when successive idle and active states follow, the output voltage is higher than VBAT 100 (input voltage) in the case of a boost power converter while working in different output voltage domains.
Arranging the power switches according to the example of FIG. 1, however, does not solve the problem. In such arrangements of power switches, the start time is still too long if the soft-start methodology is accomplished in a traditional way since when such a methodology is enabled, its internal soft-start reference voltage still starts from zero and proceeds up to the external reference voltage. Further, when a coefficient of voltage ramp is normally constant, the output voltage starts to increase just after the internal reference voltage is reaching the pre-charged output voltage. Another phenomenon is that even though the output voltage is pre-charged as configured in the example of FIG. 1, it may be discharged if the control circuitry tries to make the converter output voltage follow from 0V starting internal reference voltage. This further leads to an extra charging current needed to compensate for the energy lost under pre-charged voltage decreased.
For example, commercial chips EL7581 and LT1946A are used in this field. In EL7581, an external capacitor controls the start-up time constant. Another solution is related to a chip called TPS6734I which relies to the same as the above and to some further additions. The soft-start clamp circuit limits the signal level on error-amplifier output during start-up. The voltage on soft-start is amplified and used to momentarily override the error-amplifier output until it rises above that output, at which point the error-amplifier takes over.
In an article entitled: “Monolithically Integrated Boost Converter”, IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 20, NO. 3, MAY 2005, page 631, a special procedure during start-up is described where a large delay time is set at power up. After the delay, the output voltage is be one diode drop lower than the input voltage. The chip works in an open-loop mode until the output voltage is higher than 2.4 V. After that the soft-start is realized by slowly increasing the reference voltage. Then, during the soft start period, the output voltage is already 2.4 V for maintaining the output voltage. In the chip, the starting point of the reference voltage for the soft-start period is a fixed value of 0.8 V.
A patent publication U.S. Pat. No. 5,903,451 describes an AC-AC conversion application based on an input voltage that changes the PWM frequency of the soft start circuitry. The purpose is to provide a fast start-up time over a wide main input voltage range of 90 V up to 265 V. Another patent publication U.S. Pat. No. 6,515,880 describes a DC-DC converter having buck and boost parts included that combine load condition by its controller for producing a soft-start signal that limits the duty cycle of the power regulator switches at start-up. The duty cycle limit is gradually increased over time by operation of the signal. This solution is thus similar to the solution used in chip TPS6734I.
A patent publication U.S. Pat. No. 7,088,078 B2 describes having a soft-start circuitry reaching a predetermined value after which a soft-start period reaches its end point more rapidly. This equals having two parts to ramp up internal reference voltage slower and faster when the first output voltage has already been reached. A patent publication U.S. Pat. No. 7,106,036 describes a special power-down sequence with a combination of a delay timer and mode control that also control a soft-start circuit mode. A reset signal assertion sets a specific reference signal level. Further, a soft-start generating voltage ramp is enabled if its level is below a predetermined value. Here, focus is on modes of power-downs and the soft-start is a basic scenario.
Accordingly, improved solutions are needed where the drawbacks of the known solutions are overcome.